CLOCK GENERATOR HAVING FREQUENCY MULTIPLYING FUNCTION BASED DELAY LOCKED LOOP

摘要

A clock generator is provided to match a phase of a multiplied clock signal with a phase of a reference clock signal. A clock generator includes a DLL(Delay Locked Loop)(110), a voltage controlled delay unit(115), and a frequency multiplier(120). The DLL includes plural first delay stages which are series-connected to each other and input a reference clock signal. The DLL compares an output signal from the last delay stage with the first clock signal and adjusts the delay time of the first delay stages based on the compared result. The voltage controlled delay unit includes plural second series-connected delay stages. The voltage controlled delay unit compares the output signal from the DLL with an output from the last delay stage of the second delay stages and adjusts the delay time of the second delay stages based on the compared result. The frequency multiplier generates a multiplied clock signal having a pulse corresponding to a delay time between an output signal and a complementary output signal which is received from the voltage controlled delay unit.