| 摘要 |
Process for manufacturing a non volatile electronic device integrated on a semiconductor substrate (2) which comprises a plurality of non volatile memory cells (1) being organised in matrix and an associated circuitry, comprising the steps of:
- forming gate electrodes (7) of the memory cells (1) projecting from the semiconductor substrate (2), each of the gate electrodes (7) comprising a first dielectric layer (3), a floating gate electrode (4), a second dielectric layer (5) and a control gate electrode (6) coupled to a respective word line, at least one first portion of the gate electrodes (7) of the memory cells (1) being separated from each other by first openings (15) of a first width (D),
- forming source and drain regions (8) of the memory cells (1) in the semiconductor substrate (2), the source and drain regions (8) of the memory cells (1) being aligned with the gate electrodes (7) of the memory cells (1),
- forming gate electrodes of transistors of the circuitry projecting from the semiconductor substrate (2), each of the gate electrodes of the circuitry comprising a first dielectric layer of the circuitry and a first conductive layer of the circuitry,
- forming source and drain regions of the transistors in the semiconductor substrate (2), the source and drain regions of the transistors being aligned with the gate electrodes (7) of the transistors, the process being characterised in that it comprises the following steps:
- depositing, on the whole device, a third non conform dielectric layer (10) so as to completely fill in the first openings (15) and to form air-gaps (16) between the gate electrodes belonging to the first portion of the gate electrodes (7) of the memory cells (1).
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