| 摘要 |
A method for fabricating a saddle-type fin transistor is provided to avoid an increase of an FICD(final inspection critical dimension) by performing a fin etch process using a hard mask as spin coating polymer favorable to planarization. A substrate(210) is prepared in which an isolation layer(211) is formed. A hard mask pattern including spin coating polymer(212a) is formed on the resultant structure. A fin etch process using the hard mask pattern is performed to form a saddle-type fin. The process for forming the hard mask pattern can include the following steps. An SiON layer(212b) is deposited on the hard mask pattern. An ARC(anti-reflective coating)(213) is deposited on the SiON layer. A photoresist layer pattern(214) is formed on the ARC. An etch process is performed to etch the ARC and the SiON layer by using the photoresist layer pattern as an etch mask. The spin coating polymer is etched by using the ARC and the SiON layer that are etched by the etch process.
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