Address decoder, storage device, processor device, and address decoding method for the storage device

摘要

The address decoder includes: a plurality of decode units (13) each formed by a combinational logic circuit; an inverting circuit (16) which inverts an output of said decode unit (13); an AND circuit (14) which performs a logical AND operation between an output signal of said decode unit (13), which has been inverted by said inverting circuit (16), and another one of said plurality of decode units (13). This arrangement makes it possible to simplify the circuit construction, to improve the processing speed, and to reduce power consumption.