| 摘要 |
A method for fabricating a semiconductor device is provided to stabilize a threshold voltage by forming a P+ well of a double structure wherein the back bias voltage of a PMOS transistor constituting a latch-type sense amplifier is applied by the P+ well. An N well for forming a sense amplifier is formed on a P-type substrate, and first and second gate electrodes(27,29) are formed on the N well. Source and drain regions(35,37) are respectively formed inside and outside the first and second gate electrodes. Impurity ions are implanted into the N well at one side of the first gate electrode and the other side of the second gate electrode to form a P+ well(31,33) for applying a bias voltage. A first bitline contact(43) is formed in each P+ well. A second bitline contact is formed which comes in contact with the first and second gate electrodes. A third bitline contact(41) is formed in the source and drain regions.
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