| 摘要 |
A circuit for controlling a clock of a DLL(Delay Locked Loop) is provided to reduce a current consumption of the circuit by turning off a buffer during a precharge power down mode. A circuit for controlling a clock of a DLL includes a buffer controller(100), a falling clock output buffer(200), and a rising clock output buffer(300). The buffer controller receives a clock enable bar signal, an RAS(Row Address Strobe) idle signal, a self refresh signal, and a power up signal, and generates first and second control signals and a power down mode signal. The falling clock output buffer is driven by the first control signal. The rising clock output buffer is driven by the second control signal. The rising clock output buffer is turned off, when the power down mode signal is enabled. The buffer controller enables the power down mode signal, when the RAS idle signal is enabled. |
