STATIC TIMING ANALYSIS METHOD FOR REFLECTING EFFECTIVELY DELAY TIME OF INTERCONNECTION LINE DUE TO PARACITIC ELEMENT

摘要

A static time analysis method is provided to perform time analysis by efficiently reflecting delay time of a parasitic value of an interconnection line, and thus to perform time analysis without changing environment in the prior static timing analysis space. According to a static time analysis method for a system board comprising a first semiconductor device for transmitting data and a second semiconductor device for receiving data, a parasitic value of an interconnection line between the first semiconductor device and the second semiconductor device is obtained(S31). Total delay time of a driver of the first semiconductor device and the interconnection line is obtained(S33), by adding the parasitic value to an output stage of the driver of the first semiconductor device(S32). Delay time of the driver of the first semiconductor device is replaced with the total delay time(S34). Static time analysis on the system board including the first and the second semiconductor device is performed(S35).