| 摘要 |
A nonvolatile semiconductor memory device is provided to reduce chip size by vertically stacking a plurality of unit block cell arrays. A unit block cell array has a plurality of cell arrays stacked vertically, and the cell arrays include a plurality of unit cells arranged in rows and columns. A row address decoder(210) enables a word line of the selected cell array by decoding a row address. A vertical address decoding unit(230) selects one cell array by decoding a vertical address, and connects the output of the row address decoder to the word line of the selected cell array. A column address decoder(250) enables a bit line of the selected cell array by decoding a column address.
|
