发明名称 Chip-size package structure and method of the same
摘要 The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.
申请公布号 US7238602(B2) 申请公布日期 2007.07.03
申请号 US20040973557 申请日期 2004.10.26
申请人 ADVANCED CHIP ENGINEERING TECHNOLOGY INC. 发明人 YANG WEN KUN
分类号 H01L21/44;H01L21/56;H01L21/60 主分类号 H01L21/44
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