发明名称 Voltage tolerant protection circuit for input buffer
摘要 An improved voltage tolerant protection circuit for input buffer comprising a transmission gate circuit receiving input from the pad for passing the input signal to the input of the input buffer, a control signal generator electrically coupled between the transmission gate circuit and the pad to provide a control signal for operating the transmission gate circuit, and an N-Well generation circuit electrically coupled between the pad and the transmission gate circuit, and also electrically coupled to the control signal generator for generating a bias signal for the transmission gate circuit and the control signal generator. Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors, minimizes power supply consumption and transfers signals without any change in amplitude.
申请公布号 US7239176(B2) 申请公布日期 2007.07.03
申请号 US20050143094 申请日期 2005.06.02
申请人 STMICROELECTRONICS PVT. LTD. 发明人 GUPTA NITIN
分类号 H03K19/094;H03K19/003 主分类号 H03K19/094
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