| 摘要 |
In a DDR operation mode, (L-1) count signal BRDYB is inverted to a low level when 1 is subtracted from initial latency (e.g., L=3). As a result, a delayed signal S (N 1 BD)/S (N 1 D) in reverse phase to signal S (N 1 )/S (N 1 B) is provided and internal clock signal CKI becomes high during the high level period of the second cycle. This is operated in synchronization with both edges of the external clock signal CLK, and output of double the frequency is started. In the external clock signal cycle immediately before completion of counting of initial latency in a count period for initial latency, the internal clock signal CKI is changed over to double the frequency. Validity flag RDY is changed to a high level during a second cycle of the double frequency.
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