| 摘要 |
A method for manufacturing a semiconductor device is provided to improve contact resistance and to simplify processes by simultaneously performing an ion-implantation process into a landing plug of a cell region and an N-type junction region of a peripheral region. An NMOS transistor and a landing plug(240) are formed on a substrate(200) of a cell region(C), and an NMOS and a PMOS transistors are formed on the substrate of a peripheral region(P). By etching an interlayer dielectric, a first contact hole(H1) for exposing the landing plug and a second contact hole(H2) for exposing junction regions(210a,210b) of the NMOS and the PMOS transistors are formed. N-type impurities are implanted into the exposed landing plug and junction regions. P-type impurities are selectively implanted into the junction region of the PMOS transistor. A bit line is then formed in the first and the second contact holes.
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