METHOD FOR FABRICATING GATE OF SEMICONDUCTOR DEVICE

摘要

A method for forming a gate electrode of a semiconductor apparatus is provided to prevent generation of stress in forming the silicide layer on an upper surface of the gate electrode by forming the gate electrode having a lower portion longer than that of an upper portion. A dielectric pattern is formed on a semiconductor substrate(110). The dielectric pattern has an opening unit exposing a predetermined region of the semiconductor substrate. A gate oxide layer(112) is formed on the predetermined region of the exposed semiconductor substrate. A gate conductive layer is formed to cover the gate oxide layer and the dielectric pattern. The gate conductive layer is patterned to form a gate electrode(114a). The dielectric pattern is etched by using the gate electrode as a mask to form a spacer(120b). A silicide layer(116) is formed on the gate electrode and an upper portion of the semiconductor substrate. The length of a lower portion of the gate electrode is longer than that of an upper portion thereof.