| 摘要 |
A clock generator of a semiconductor memory device is provided to generate a reliable clock by performing phase and duty cycle compensation using divided clocks. A first frequency divider(110) divides a first internal clock by using an external clock. A first delay unit(120) delays an output from the first frequency divider by a predetermined time. A second frequency divider(140) divides a second internal clock by using the external clock. A second delay unit(150) delays an output from the second frequency divider by a predetermined time. A duty cycle compensator(160) compensates for first and second delay units and outputs first and second compensation clocks. A phase splitter(170) separates the first compensation clock from the second compensation clock and outputs the result. A third frequency divider(180) divides the first compensation clock. A third delay unit(190) delays the output from the third frequency divider by a predetermined time. A phase comparator(200) compares the outputs from the third delay unit and the first frequency divider with each other and outputs the result. A delay unit setter(220) sets the delay time for the first and second delay units according to the output from the phase comparator.
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