发明名称 METHOD FOR MANUFACTURING METAL LINE AND INTERMETAL DIELECTRIC LAYER
摘要 A manufacturing method of a metal wiring and an interlayer dielectric is provided to reduce void and clipping phenomenon when depositing the interlayer dielectric through HDPCVD by appending a dummy wiring into a region where the metal wiring is formed with high density and low density. A semiconductor device and a lower interlayer dielectric are formed on a semiconductor substrate(100). A metal wiring having a high density wiring region(120) and a low density wiring region(140) is formed on the lower interlayer dielectric, and a dummy wiring(108) is formed between the high and low wiring regions. An upper interlayer dielectric(106) is formed on the lower interlayer dielectric by performing HDPCVD.
申请公布号 KR20070069983(A) 申请公布日期 2007.07.03
申请号 KR20050132757 申请日期 2005.12.28
申请人 DONGBU ELECTRONICS CO., LTD. 发明人 LEE, TAE YOUNG
分类号 H01L21/28;H01L21/205;H01L21/3205 主分类号 H01L21/28
代理机构 代理人
主权项
地址
您可能感兴趣的专利