| 摘要 |
A latch circuit of a semiconductor memory device is provided to improve an operation reliability of the semiconductor memory device by removing a glitch from an output signal in the latch circuit. A latch circuit of a semiconductor memory device includes a latch unit(100), an output unit(200), and an output unit controller(300). The latch unit receives first and second input signals and latches a combined level of the first and second input signals. The output unit inverts the output level from the latch unit and outputs the inverted level. The output unit controller disconnects a current path from the output unit, when the first and second input signals are activated. The latch unit includes a NOR gate and an inverter. The inverter receives the signal from the NOR gate and outputs the inverted signal to a node, where the first input signal is applied. |
