| 摘要 |
A method for fabricating a semiconductor device is provided to decrease parasitic capacitance of a bit line by increasing a distance between a gate and the bit line, thereby improving a device characteristic. Plural gate patterns(33) composed of a gate electrode and a gate hard mask are formed on a semiconductor substrate(31). A sidewall of the gate electrode is etched by isotropic etching to have a recessed lateral profile, and then is subjected to light oxidization to form an oxide layer on the sidewall of the gate electrode. A gate spacer is formed on the entire surface of the substrate comprising the oxide layer.
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