| 摘要 |
A latch circuit in a semiconductor memory device is provided to reduce current consumption amount by disabling the signals, which are applied to eight pads and one data strobe pad in no use, when the width of data is x8. A latch circuit in a semiconductor memory device includes a data strobe buffer, a delay unit, a pulse generator, a data input buffer, a set-up/hold time adjusting unit, and a data input latch unit. The data input latch unit includes a controller(100), a data sense amplifier(200), and an output unit(300). The controller combines one of first and second pulse signals with a selection signal and outputs a control signal. The data sense amplifier changes the voltage levels of first and second nodes by sensing and amplifying a voltage level difference between a data signal and a data bar signal, when the control signal is enabled. The output unit selects one of a source voltage and a ground voltage according to the voltage levels of the first and second nodes, latches the selected voltage, and outputs the result as a data output signal.
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