发明名称 SALLOW TRENCH ISOLATION IN SEMICONDUCTOR AND MANUFACTURING METHOD OF THEREOF
摘要 An isolation region of a semiconductor device and a method for forming the same are provided to prevent moat caused by over-etching of an edge portion by forming the isolation region using a selective etch process. A sacrificial oxide layer and a sacrificial nitride layer are stacked on a semiconductor substrate(100) having an edge region(E) and a center region(C). A first trench(T1) and a second trench(T2) are formed in the edge region and the center region, respectively by etching the sacrificial nitride layer, the sacrificial oxide layer and the substrate using a selective etch process. An oxide layer is filled in the first and the second trenches. By polishing the oxide layer to expose the sacrificial layer of the edge region, a first isolation region(108) is formed in the first trench and a second isolation pattern is formed. A second isolation region(110) is formed by etching the second isolation pattern using a photoresist pattern. At this time, the second isolation region is thicker than the first isolation region.
申请公布号 KR20070069686(A) 申请公布日期 2007.07.03
申请号 KR20050132089 申请日期 2005.12.28
申请人 DONGBU ELECTRONICS CO., LTD. 发明人 PARK, KEUN SOO
分类号 H01L21/76 主分类号 H01L21/76
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