发明名称 Simultaneous planar and non-planar thin-film transistor processes
摘要 A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.
申请公布号 US7238554(B2) 申请公布日期 2007.07.03
申请号 US20040985587 申请日期 2004.11.09
申请人 发明人
分类号 H01L21/00;H01L29/10;H01L29/76;H01L29/786 主分类号 H01L21/00
代理机构 代理人
主权项
地址