METHOD FOR LAYOUT DESIGN REFLECTING TIME DELAY EFFECT FOR DUMMY METAL FILL IN SEMICONDUCTOR DEVICE

摘要

A method for layout design reflecting a time delay effect by a dummy metal fill in a semiconductor device is provided to design the semiconductor in the more exact manner by using a layout parasitic parameter. Logic gates such as transistor level cells automatically placed and routed in a placement & routing (P & R) process(20). Resistor capacitance values of a wiring formed between logics are extracted in a layout parasitic parameter extract process(30). The resistor capacitance(RC) is used to confirm whether or not to operate in a desired specification in a static timing analysis process(40). In a graphic data system II(GDSII) layout versus schematic(LVS)/design rule checker(DRC) check process(40a), which is simultaneously performed with the static timing analysis process, it is checked whether or not the layout and the circuit diagram are equal to each other. A metal fill pattern for dummy metal is formed and then an edge of the metal fill pattern is corrected in an OPC(Optical Proximity Correction) and metal fill pattern generation process(50). The metal fill pattern is applied to the layout parasitic parameter extract process to extract an updated RC of an updated wiring in a real-metal fill pattern application process. After a time delay effect due to the real-metal fill pattern is reflected, the above processes are repeated.