| 摘要 |
PROBLEM TO BE SOLVED: To provide a ferroelectric storage device which improves a sense margin accompanying the reduction of a cell array degree of integration and bit line capacity. SOLUTION: The ferroelectric storage device includes main bit lines MBL1 and MBL1b; sub-bit lines SBL1 and SBL1b; a ferroelectric capacitor; memory cells which are provided at positions at which a word line crosses the SBL1 and the SBL1b; a transistor TR1 which connects the SBL1 with the MBL1; a transistor DTR1 which grounds the sub-bit line SBL1; a transistor TR1b which connects the sub-bit line SBL1b with the MBL1b; a transistor DTR1b which grounds the SBL1b; a selection line BLSEL1 which is connected in common to each of the gates of the TR1 and DTR1b; a selection line BLSEL1b which is connected in common to each of the gates of the DTR1 and TR1b; a plate line PL1 to which the memory cell of the SBL1 is connected; and a plate line PL2 to which the memory cell of the SBL1b is connected. COPYRIGHT: (C)2007,JPO&INPIT
|
