| 摘要 |
A True Single Phase Clock flip-flop is configured to operate in an evaluating and a hold mode. The flip-flop comprises an input stage having an input node and a first output node. The flip-flop further comprises a middle stage having a second output node and an output stage having a third output node. The flip-flop further comprises a reset functional block which is switchable between an activated and a deactivated mode. Said reset functional block resets said flip-flop when activated and is configured to synchronous exit out of reset when switched from its activated to its deactivated mode so that an output signal of said flip-flop is only up-dated when said flip-flop changes to its next evaluating mode.
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