发明名称 Method, apparatus, and systems to support execution pipelining in a memory controller
摘要 A memory controller may execute instructions instead of sending the instructions to a processor for execution. To maintain synchronization between the memory controller and the processor, the memory controller may queue a null instruction in the memory controller for each non-filler instruction sent to the processor and may send a filler instruction to the processor for each non-null instruction to be executed by the memory controller.
申请公布号 US2007150673(A1) 申请公布日期 2007.06.28
申请号 US20060372647 申请日期 2006.03.10
申请人 RAJARAM G 发明人 RAJARAM G.
分类号 G06F13/00 主分类号 G06F13/00
代理机构 代理人
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