MULTI-PROCESSOR CIRCUIT WITH SHARED MEMORY BANKS

摘要

A plurality of processors (10) in a multiprocessor circuit is coupled to a plurality of independently addressable memory banks (12) via a connection circuit (14). The connection circuit is arranged to forward addresses from a combination of the processors (10) to addressing inputs of memory banks (12) selected by the addresses. The connection circuit (14) provides for a conflict resolution scheme wherein at least one of the processors (10) is associated with an associated one of the memory banks (12) as an associated processor. The connection circuit (14) guarantees the associated processor a higher minimum guaranteed access frequency to said associated one of the memory banks (12) than to a further one of the memory banks (12) other than the associated one of the memory banks (12). A defragmenter (16) detects data associated with a task running on the associated processor (10) that is stored on the further one of the memory banks (12) and move said data to the associated one of the memory banks (12) during execution of the task. The defragmenter cause addressing of the data by the associated processor (10) to be remapped from said further one of the memory banks (12) to the associated one of the banks after said moving, preferably incrementally as movement of data progresses.