发明名称 PLANAR VOLTAGE CONTRAST TEST STRUCTURE AND METHOD
摘要 <p>An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.</p>
申请公布号 SG132667(A1) 申请公布日期 2007.06.28
申请号 SG20070032345 申请日期 2004.09.09
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD. 发明人 KEONG VICTOR LIM SENG;TAN DENNIS;HO SIMON CHAN TZE
分类号 G01R31/28;G01R31/307 主分类号 G01R31/28
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