| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress occurrence of an abnormal clock signal at reset and at application of power in particular as to PLL circuits connected in series. <P>SOLUTION: In the PLL circuit comprising the two PLL circuits (10A, 20) connected in series, the pre-stage PLL circuit (10A) includes: a voltage controlled oscillator (104) for generating an output clock signal; and a control voltage detection circuit (106) that detects whether or not a control voltage received by the voltage controlled oscillator (104) is within a prescribed range and outputs a detection signal denoting a result of the detection. The post-stage PLL circuit (20) is halted when the detection signal outputted from the pre-stage PLL circuit (10A) is at a first logic level, and on the other hand, when the detection signal is at a second logic level, the post-stage PLL circuit (20) is activated. <P>COPYRIGHT: (C)2007,JPO&INPIT |
