<p>An apparatus includes a multi-cycle clock gater (20) and a circuit design updater (22). The multi-cycle clock gater (20) generates multi-cycle gating groups of data latching devices of a circuit design. The circuit design updater (22) updates the circuit design with selected multi-cycle gating groups. Each gating group is associated with a single gating function. For each gating group, data latching devices of 0th level of the gating group are gated with the gating function and ith level data latching devices of the gating function are gated with ith latched versions of the gating function.</p>
申请公布号
WO2007071506(A1)
申请公布日期
2007.06.28
申请号
WO2006EP68582
申请日期
2006.11.16
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;EISNER, CYNTHIA;FARKASH, MONICA