| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a bit line clamp voltage generating circuit wide in an operation voltage margin. <P>SOLUTION: The bit line clamp voltage generating circuit 14 includes: a current mirror circuit 20 having an input stage n1 and an output stage n2; a resistor dividing circuit 22 provided between the input stage n1 and a first reference potential VSS; a potential setting circuit 24 provided between an output n3 and the output n2 of the resistor dividing circuit 22; and an operational amplifier 28 constituted by using transistors other than intrinsic type transistors. The bit line clamp voltage BLCLAMP is obtained from the output stage n2 of the current mirror circuit 20. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
