发明名称 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE
摘要 A semiconductor memory device includes a memory cell array, a bit line, a precharge circuit and a first sense amplifier. The memory cell array includes memory cells. The bit line connects commonly the memory cells in the same column. The precharge circuit applies a precharge potential to the bit line in reading data. The first sense amplifier amplifies data read onto the bit line. The precharge circuit determines the data read on the bit line using as a reference potential the precharge potential applied to the bit line by the precharge circuit.
申请公布号 US2007147128(A1) 申请公布日期 2007.06.28
申请号 US20060613492 申请日期 2006.12.20
申请人 EDAHIRO TOSHIAKI 发明人 EDAHIRO TOSHIAKI
分类号 G11C16/06;G11C7/02;G11C11/34 主分类号 G11C16/06
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