| 摘要 |
PROBLEM TO BE SOLVED: To generate an excellent vertical synchronizing signal without generating an erroneous vertical synchronizing signal, even when an erroneous vertical synchronizing pulse is detected depending on a noise state. SOLUTION: When a video signal PS is input and a vertical synchronizing pulse detecting circuit 11 erroneously detects a vertical synchronizing signal HSP in the video signal PS; a matching confirming detection result S14 of a synchronization stability detecting circuit 14 indicates discrepancy. The detecting circuit is used for detecting whether a detection signal S11 of the detecting circuit 11 matches a timing signal S13 generated from a count value S12 of a frame cycle counter 12. Therefore, since the count value S12 of the frame cycle counter 12 is not loaded to a frame cycle counter 15, a vertical synchronizing signal HS can be generated with a previously detected normal phase by operations of the frame cycle counter 15, a timing generating decoding circuit 16, and a vertical synchronizing signal generating circuit 17. COPYRIGHT: (C)2007,JPO&INPIT
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