发明名称 SEMICONDUCTOR DESIGN SUPPORT DEVICE
摘要 PROBLEM TO BE SOLVED: To much more highly precisely verify a layout pattern in a layout verification process. SOLUTION: This layout pattern verification device is provided with a pattern data generation part, a layout performance part, and a layout verification part. The pattern data generation part forms a recognition pattern (40) in a region (44) having a first symmetric axis (45) and a second symmetric axis (46) vertical to the first symmetric axis (45). The recognition pattern (40) is configured asymmetrically to the first symmetric axis (45) and the second symmetric axis (46). The layout performance part generates the layout pattern data (22) by determining the layout of a microcell (24) having the recognition pattern (40). A layout verification part reads the pattern data of the recognition pattern (40) included in the microcell (24) based on the layout pattern data, and verifies the arranging direction of the microcell based on the status of the recognition pattern. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007164231(A) 申请公布日期 2007.06.28
申请号 JP20050355814 申请日期 2005.12.09
申请人 NEC ELECTRONICS CORP 发明人 HINO FUMIKO
分类号 G06F17/50 主分类号 G06F17/50
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