发明名称 Method of forming isolation layer of semiconductor device
摘要 There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer by forming a chemical mechanical polishing (CMP) stop layer on an isolation layer having a relatively large region and performing a planarization process using the CMP stop layer. In accordance with an embodiment of the present invention, an isolation layer is completed by: forming a buffer insulating layer on a silicon substrate and patterning the buffer insulating layer; selectively etching the silicon substrate and forming trenches including a relatively big region and a relatively narrow region; depositing a first insulating layer and a second insulating layer sequentially on a whole surface of the silicon substrate; selectively removing the second insulating layer and forming a chemical mechanical polishing (CMP) stop layer only on the relatively large trench region; planarizing the first insulating layer using the CMP stop layer; and removing all of the CMP stop layer and the buffer insulating layer and completing an isolation layer.
申请公布号 US2007148907(A1) 申请公布日期 2007.06.28
申请号 US20060642546 申请日期 2006.12.21
申请人 DONGBU ELECTRONICS CO., LTD. 发明人 KANG MYUNG IL
分类号 H01L21/762 主分类号 H01L21/762
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