发明名称 BUS ARBITRATION CIRCUIT AND MULTILAYER BUS SYSTEM USING IT
摘要 PROBLEM TO BE SOLVED: To enable a specified bus master to surely make a fixed amount or more of access in a fixed period. SOLUTION: When an access request is simultaneously generated from a plurality of master connection ports 11-13 to one slave connection port 15A, the access (access request signals S21-2 and S21-3) from the master connection ports 12 and 13 of low priority is masked by AND gates 23 and 24 inside the slave connection port 15A, and the access (access request signal S21-1) from the master connection port 11 (of high priority) demanding real time processing is preferentially selected by the output signals S22g of a bus control circuit 22. When the number of times of transfer demanded in the real time processing is completed within the fixed period, the access from the other master connection port 12 or 13 is preferentially selected by the output signals S22g. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007164428(A) 申请公布日期 2007.06.28
申请号 JP20050359205 申请日期 2005.12.13
申请人 OKI ELECTRIC IND CO LTD 发明人 KAMEGAWA HIDEKI
分类号 G06F13/362 主分类号 G06F13/362
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