| 摘要 |
1325099 Semi-conductor devices WESTERN ELECTRIC CO Inc 30 Sept 1971 [5 Oct 1970] 45487/71 Heading H1K A charge storage device comprises, in a single semi-conductor body, a plurality of elements each having a source and a drain and first and second gate electrodes disposed between them, each drain being common to a plurality of sources and each second gate being common to a plurality of sources or connected to the second gate associated with another source. The gates are so disposed that both have to be similarly poled to provide a current path between source and drain. Although in the described arrangements the sources and drains are P-type diffusions in an N-type silicon substrate and insulated gates are used the use of PN or Schottky barrier gates, MOS sources and Schottky barrier drains is also envisaged. The elements may act as photodetectors in an imaging device. In this case with a source floating illumination near it causes it to collectminority carriers which are transferred to the drain by biasing both gates on to give an output indicative of light intensity. When used simply as a memory cell information is fed in by transferring a potential on the drain indicative of a binary 0 or 1 to the source by biasing the gates on. During read-out the drain current is indicative of the stored binary state. A line imaging device is shown in plan in Fig. 2. Sources 11 are floating, first gates 14 connected in groups to one of the outputs of shift register 22, second gates 15 to outputs of shift register 23, and the drain to a load circuit. The elements are scanned by reading pulses applied to gates 14, 15 from the shift registers such that the pulses are coincident on each element in turn. In a modification the elements form an X-Y array, with the drains and the first gates of all elements in a column respectively commoned, as are the second gates of all elements of a row. Read-out of an nÎn array is effected by column and row scan registers each consisting of a pair of shift registers with #n outputs. Output capacitance is minimized by connecting an IGFET in series with each column of elements. |
