发明名称 |
PIPELINE ARCHITECTURE FOR VIDEO ENCODER AND DECODER |
摘要 |
<p>An image data-processing apparatus (100) includes an image data-decoding unit (10) operable to execute pipeline processing-assisted image decoding processing, a pipeline controller (20) operable to control pipeline processing in the image data-decoding unit (10), a memory (30), and an input/output interface (40). The pipeline controller (20) executes control over the pipeline processing on the basis of information on the start-up of pipeline stages. The information is stored in a start-up table storage unit (23). The present configuration makes it feasible to provide an image data-processing apparatus operable to suppress degradation in decoded images to a minimum degree when pipeline control is disturbed upon the occurrence of decoding errors during the decoding processing, whereby high-quality images are realized.</p> |
申请公布号 |
EP1800489(A1) |
申请公布日期 |
2007.06.27 |
申请号 |
EP20050790417 |
申请日期 |
2005.09.30 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KONDO, TAKAHIRO |
分类号 |
H04N19/50;G06F9/38;G06F11/07;H04N19/423;H04N19/436;H04N19/44;H04N19/503;H04N19/60;H04N19/61;H04N19/625;H04N19/895;H04N19/91 |
主分类号 |
H04N19/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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