| 摘要 |
A method for fabricating a transistor in a stacked cell structure is provided to reduce contact resistance by increasing the area of a source/drain contact surface without increasing the thickness of a layer in which a channel region is formed. An active layer(3) is formed on a substrate having a lower transistor. A part of the active layer is etched to form an opening. An insulation layer spacer is formed on the sidewall of the opening, exposing a part of the active layer exposed from the opening. A gate insulation layer and a gate electrode(10') are sequentially formed on a part of the exposed active layer. A source/drain region is formed in the active layer in the periphery of the gate electrode. An interlayer dielectric(2) is formed on the gate electrode and the active layer. A source contact hole and a drain contact hole are formed which penetrate the interlayer dielectric and the source/drain region. The source contact hole and the drain contact hole are filled with a conductor. A first layer(3a) and a second layer(3b) can be alternately and repeatedly formed in the active region wherein the first layer is made of a silicon layer and the second layer is made of a silicon germanium layer.
|
