| 摘要 |
A write data path (400, fig 6) for an array of memory cells receives a serial burst of data bits from an external terminal (426, fig 6) and stores these bits in a corresponding number of buffers (422, fig 6). The data in the buffers is then transferred to memory cell array (410, fig 6) using two sequential parallel transfers from half of the buffers and then the other half by connecting the buffers to the common data lines (412, fig 6) through switches (424, fig. 6). In alternative arrangements the buffers can be provided as a first and a second buffer (432a, 432b fig 7) with corresponding serial to parallel converters (430a, 430b fig 7) or the first and second buffers (442a, 442b fig 8) which can be connected by the first switching circuit (446a fig 8) with the second switching circuit (446b fig 8) connecting the second buffer to the memory cell array. An additional circuit is provided to compare an address associated with a read command with an address of a preceding write operation; if the two addresses match the read operation is fulfilled using data latched in an additional data latch 2016. If the two addresses do not match then the read command is fulfilled by accessing the data in the memory cell array. The additional circuit comprises an address latch 2012, address comparison circuit 2014 and data latch 2016. |
