| 摘要 |
An FFT operation circuit is provided to reduce power consumption by handling a plurality of FFT lengths without the plurality of operation circuits corresponding to a radix so removing the number of circuits. A signal sequence converter reads a signal in a sequence that butterfly operators perform complex multiplication and subtraction/addition. A complex multiplication part(30) performs the complex multiplication of each signal read by the signal sequence converter, which sequentially reads the FFT length and a complex coefficient corresponding to each stage number of the butterfly operators. A complex adding/subtracting part(32) sequentially performs the complex addition/subtraction of the signal complex-multiplied by the complex order output from the complex multiplication part. A butterfly selector selects and outputs of operation results of the butterfly operators for the FFT length.
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