发明名称 TEST APPARATUS, REGULATING APPARATUS, REGULATING METHOD, AND COMPUTER READABLE MEDIUM ON WHICH REGULATING PROGRAM IS RECORDED
摘要 A test apparatus, a regulating apparatus and method, and a computer readable medium on which a regulating program is recorded are provided to regulate the phase difference(skew) of signal input/output in each port of each signal input/output part to be equal even when the line length from each port to a connection point of each signal input/output part is different. In a test apparatus for testing a device, a plurality of signal input/output parts includes a signal output part for outputting a signal to a port of the device and a signal input part for inputting a signal output from the port. A first regulating part(400) regulates such that the phase difference from signal output of the signal output part to signal input of the signal input part in each signal input/output part is approximately equal to those of other signal input/output parts. A shift detection part(410) detects a first shift of shifting signal input timing of the signal input part such that the signal input part of the second signal input/output part inputs the signal outputted from the signal output part of the first signal input/output part, and a second shift of shifting signal input timing of the signal input part such that the signal input part of the first signal input/output part inputs the signal outputted from the signal output part of the second signal input/output part. A calculation part(450) calculates the phase difference between the first and the second signal input/output part, on the basis of the first shift and the second shift. A second regulating part(480) regulates such that the signal input and output phases of the first and the second signal input/output part are approximately equal, on the basis of the phase difference.
申请公布号 KR20070065211(A) 申请公布日期 2007.06.22
申请号 KR20060105596 申请日期 2006.10.30
申请人 ADVANTEST CORPORATION 发明人 MATSUBARA YASUO;TAKASAKI MANABU
分类号 G11C29/00;G11C7/10 主分类号 G11C29/00
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