| 摘要 |
An interfacing network for providing asynchronous data transfers directly with a computer memory and external devices. Computer instructions from the computer arithmetic unit are decoded in an executive control unit. Certain instructions ready an input or output channel control unit which thereafter controls data transfers with a selected external device. Each transfer is made directly with the computer memory and does not require interruption of the program being processed in the arithmetic unit. Once the input or output channel control unit assumes control of the transfer, the executive control unit is immediately available to perform other functions independently and concurrently. It may ready the other channel control unit and monitor external device and interface conditions including the readiness of an external device to transmit data. Certain monitored conditions cause the interfacing network to interrupt normal computer operation. Various control signals in the executive control unit are translated to and from control signals in the computer and external devices to permit the utilization of common instructions.
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