| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a layout design method capable of preventing malfunction caused by a clock skew, and allowing easy materialization. <P>SOLUTION: This layout design method has: a step (a) for setting a connection state of clock signal wiring lines such that a clock signal is supplied toward a first terminal of a flip-flop on a data input side from a second terminal of a flip-flop on a data output side by use of a cell library defined with the second terminal for outputting the clock signal and the first terminal for inputting the clock signal to the flip-flop to create a net list; a step (b) for automatically creating layout on the basis of the net list and the cell library; and a step (c) for replacing the first and second terminals of the respective flip-flops with one clock signal input terminal to correct the layout created in the step (b). <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
