发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN PROGRAM AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the area of a semiconductor integrated circuit in a semiconductor integrated circuit design method, a semiconductor integrated circuit design program, and a semiconductor integrated circuit with a layout determined thereby. SOLUTION: In S104 of Fig. 1, each signal line is disposed in a signal wiring position having a predetermined positional relation with any one of wiring grids. In S102, layout of signal lines is determined so that when a signal line is disposed in a signal wiring position closest to a power supply line of signal wiring positions located outside the power supply line, the distance between this signal line and this power supply line is a predetermined shortest distance D to be ensured between signal line and power supply line or more, and the distance between mutually adjacent power supply lines corresponds to an added length of a double-length of D and an integral multiple of an added length of a predetermined shortest distance to be ensured between signal lines and the respective signal line widths. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007156985(A) 申请公布日期 2007.06.21
申请号 JP20050353733 申请日期 2005.12.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKANO MISAO;TANAKA TOSHIYUKI;MATSUTANI TSUGIKO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
代理机构 代理人
主权项
地址