| 摘要 |
A flat panel display includes pixel circuits, a signal divider for associating portions of the image signal with corresponding portions of the pixel circuits, and timing controller circuitry for receiving the portions of the image signal and outputting corresponding sets of control signals and pixel data, the timing controller circuitry outputting the sets in parallel. The flat panel display includes groups of data drivers, each group for receiving respective sets of control signals and pixel data from the timing controller circuitry and driving corresponding pixel circuits, different groups receiving the sets in parallel.
|
