POWER MOSFET AND METHOD OF MAKING THE SAME

摘要

A MOS device (40, 70) comprising first and second N-type source regions (50), electrically in parallel, located in spaced-apart P- type body regions (46), separated by an N-type JFET region (56) at a first surface (45). Channel regions (47) underlying the gate (53) at the first surface (45), extend from the source regions (50) through portions (47) of the body regions (46) to the JFET region (56) which communicates via an N-epi region (44) with an underlying drain region (42). Ion implantation is used to tailor the doping density (86, 92) in the JFET region (56) so that the net active doping concentration (86, 92) in a central portion (X{?) of the JFET region (56) decreases substantially linearly from the first surface (45) toward the underlying N epi region (44). A thickened gate dielectric layer region (72) may be provided on said control portion of the JFET region (56).