| 摘要 |
A semiconductor substrate manufacturing method, including: forming, on an active surface side of a semiconductor base material, a first semiconductor layer whose etch selectivity is higher than that of the semiconductor base material; forming over the first semiconductor layer a second semiconductor layer whose etch selectivity is lower than that of the first semiconductor layer; forming a support hole so as to expose the semiconductor base material by partially removing and opening the second and first semiconductor layers around an element region; forming a support formation layer on the active surface side of the semiconductor base material by filling the support hole and covering the second semiconductor layer; forming, through etching, an opening surface that exposes part of end portions of a support and the first and second semiconductor layers located under this support, leaving a region including at least part of a region for the support hole and the element region; forming a cavity between the second semiconductor layer of the element region and the semiconductor base material by selectively etching the first semiconductor layer via the opening surface; forming a buried insulating film in the cavity; forming a planarized insulating film on the active surface side of the semiconductor base material; and removing, after planarizing the active surface side of the second semiconductor layer, the support formation layer remaining at a position where it covers the second semiconductor layer or at least part of a layer derived from the planarized insulating layer so as to expose the element region; wherein, when the selective etch is performed while keeping a maximum width of the element region to be narrower than a width expressed as 2xSxR in which S is a tolerable etch amount of the second semiconductor layer that is etched simultaneously with the first semiconductor layer in the selective etch, and R is a selectivity between the first semiconductor layer and the second semiconductor layer in the selective etch, the first semiconductor layer is removed in a state that a parasitically etched amount of the second semiconductor layer is kept at the tolerable etch amount S or less.
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