发明名称 METHOD AND SYSTEM FOR INCORPORATION OF PATTERNS AND DESIGN RULE CHECKING
摘要 Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes "known good" patterns, which chip fabricators know from experience are successful, and "known bad" patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.
申请公布号 WO2006127485(A3) 申请公布日期 2007.06.21
申请号 WO2006US19509 申请日期 2006.05.19
申请人 CADENCE DESIGN SYSTEMS, INC.;SCHEFFER, LOUIS, K.;NOICE, DAVID, C. 发明人 SCHEFFER, LOUIS, K.;NOICE, DAVID, C.
分类号 G06F17/50 主分类号 G06F17/50
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