| 摘要 |
<p>A class-D amplifier is provided to enlarge a dynamic range without increasing a clock frequency of PWM(Pulse Width Modulation) circuit. A class-D amplifier includes an input terminal(1), a PWM circuit(12), a delay tap circuit(14), and a selector(15). The input terminal(1) sets a bit number of input data as 15 bit and the input data is inputted in the input terminal(1). The PWM circuit(12) sets the bit number of an inner circuit as 10 bit and the upper 10 bit of the input data is inputted in the PWM circuit(12). Master clocks are inputted in the PWM circuit(12) and the delay tap circuit(14). The delay tap circuit(14) converts the master clocks to clock pulses. The clock pulses are outputted to the selector(15). The selector(15) selects one of clock pulses and outputs one selected clock pulse to the PWM circuit(12) based on lower 5 bit of the input data.</p> |
