发明名称 Filling narrow and high aspect ratio openings using electroless deposition
摘要 Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.
申请公布号 US2007141826(A1) 申请公布日期 2007.06.21
申请号 US20050303560 申请日期 2005.12.15
申请人 INTEL CORPORATION 发明人 CHOWDHURY SHAESTAGIR;TSANG CHI-HWA
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 代理人
主权项
地址