ARITHMETIC UNIT WITH WAITING MECHANISM

摘要

An arithmetic unit in which waiting of a plurality of elements of data inputted to respective processor elements is performed locally, and programming needs not to take account of synchronization of data. The arithmetic unit comprises one or more first processor elements, one or more second processor elements, and a waiting means, wherein the waiting means has a payload for holding data outputted from the first processor elements, respective, and a flag corresponding to the payload and indicating whether a corresponding payload is in valid state or invalid state. The flag takes a valid state when a first processor element writes data in the corresponding payload, and takes an invalid state when all second processor elements receiving that data read out the data from the payload.